Industry-Standard Hypercomputer Chips

Convergence of MetaCalculus and Hardware Design

With today's many-core chips, the IMS RISC approach to MetaComputer emulation is converging toward a mainstream channel of software migration into hardware design. As most languages today are virtual-machines (MetaComputers without ASIC and ASSP hardware enhancement), they will take on the performance leverage of compiled languages like C, C++, Ada, and Fortran on this architecture, and with the MetaCalculus ASSP-enhanced pseudo-machine as standard semantics, all of them will become MetaCalculus languages.

Standard MetaComputer Emulation Host Architecture

Our original RISC design (24 instructions) could be the core-design for a standard family of many-core chips (16, 32, 64, 128, 256 cores, etc.) that would be software provisioned by the kind of high-level software automation started at the Aerospace Corporation. This automation scaffolding is now part of the MetaCalculus AutoLab as the tools: EverGlade, GAEMY, and Spiritext. They are designed to radically reduce OS, language, and GUI development effort, facilitating decentralized hypercomputer tailoring to vertical application domains and integrated embedded computer markets.

The proposed plan could be implemented by an international non-profit industry hardware/software consortium, somewhat like the IntelliCAD Technology Consortium. This hardware could stimulate market conditions similar to when the PC-AT open ISA bus expanded market growth out from under IBM. Now software/hardware integration firms like traditional Unix VARs could produce new hypercomputer products tailored to their vertical markets.